SPICE Device Model SUD40N04-10A Vishay Siliconix N-Channel 40-V (D-S) 175C MOSFET CHARACTERISTICS * N- and P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71751 19-Oct-01 www.vishay.com 1 SPICE Device Model SUD40N04-10A Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Simulated Data Symbol Test Conditions VGS(th) VDS = VGS, ID = 250A 2.1 VDS = 5 V, VGS = 10 V 568 Measured Data Unit Static Gate Threshold Voltage a On-State Drain Current ID(on) a Drain-Source On-State Resistance a Forward Transconductance rDS(on) V VGS = 10 V, ID = 40A 0.0072 0.0075 VGS = 10 V, ID = 40 A, TJ = 125C 0.011 0.012 VGS = 10 V, ID = 40 A, TJ = 175C 0.013 0.015 VGS = 4.5 V, ID = 10 A 0.011 0.011 VGS = 4.5 V, ID = 10 A, TJ = 125C 0.016 0.018 VGS = 4.5 V, ID = 10 A, TJ = 175C 0.018 0.022 A gfs VDS = 15 V, ID = 40 A 55 40 S a VSD IS = 40 A, VGS = 0 V 0.91 1 V Input Capacitance Ciss 1771 1700 Output Capacitance Coss 382 370 Reverse Transfer Capacitance Crss 139 145 Total Gate Chargec Qg 32 35 Forward Voltage Dynamic b c VGS = 0 V, VDS = 25 V, f = 1 MHz Gate-Source Charge Qgs 6 6 Gate-Drain Chargec Qgd 8 8 Turn-On Delay Time c td(on) 10 14 14 7.5 19 30 25 14 21 30 c tr Turn-Off Delay Time c td(off) Rise Time Fall Time c tf Reverse Recovery Time trr VDS = 20 V, VGS = 10 V, ID = 40A VDD = 20 V, RL = 0.50 ID 40 A, VGEN = 10 V, RG = 2. IF = 40 A, di/dt = 100 A/s pF nC ns Notes a. Pulse test; pulse width 300 s, duty cycle 2% b. Guaranteed by design, not subject to production testing c. Independent of operating temperature. www.vishay.com 2 Document Number: 71751 19-Oct-01 SPICE Device Model SUD40N04-10A Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 71751 19-Oct-01 www.vishay.com 3